Today's printed circuit board (“PCB”) designs are increasingly complex and make use of industry standards and interfaces (e.g., dual data rate (“DDRx”), High-Definition Multimedia Interface (“HDMI”), etc.). The interfaces contain scalable interconnectivity definitions. Schematic, topology, and even PCB layout environments have adapted to compressing connectivity into hierarchical elements like net groups and buses. However, while interconnects have evolved to display and manage hierarchy, in existing systems blocks or symbols in electronic circuit design topology editors are either single pin or multi-pin. In a single pin topology all symbols have predetermined pins, one for each connection. These topologies offer a view of all of the connectivity but are often very complicated and difficult to manage. Multi-pin topologies support blocks where the connections between blocks can be comprised of multiple signals. These topologies allow for entire interfaces to be captured but also require a protocol to define block to block connectivity and lack connectivity details.